1. Field of the Invention
The embodiments relate to junction field effect transistors (JFETs), and more specifically, to an asymmetric semiconductor-on-insulator junction field effect transistor (SOI JFET), a method of forming such an asymmetric SOI JFET, and a design structure for the SOI JFET.
2. Description of the Related Art
Recently, symmetric dual-gate and wrapped-gate junction field effect transistors (JFETs) have been developed. Advantages associated with dual-gate JFETs include a relatively large conduction area for a high on-current and tight channel region control for a low off-current, as compared to single-gate JFETs. Advantages associated with wrapped-gate JFETs include an even larger conduction area for a high on-current and even tighter channel region control for a low off-current. However, there is a need in the art for improvements to these JFET structures in order to reduce lateral dimensions and/or optimize source-to-channel link-up.